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Semiconductor and Electronic Failure Analysis Blog

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A Day in the Electronic Failure Analysis Lab

A Typical Day in the Life of a Failure AnalystEvery morning in the failure analysis lab holds the potential for a new challenge. A board from a missile guidance system, an integrated circuit from the latest cell phone or video game console, or pieces of a high tech neural implant may be but a few of the many different devices that analysts may find waiting on their desks in the morning (after, of course, a requisite stop at the coffee pot – like many other engineering fields, xanthic alkaloids are one of the cornerstones of a healthy analyst’s diet).

Though there is a vast range of device types that may cross an electroic failure (FA) analyst’s desk, there are similarities between every FA project that can be examined; regardless of the unique circumstances of a given electroic device, there are still a handful of standard steps that come together to make up a typical day in the electronic failure analysis lab.

In many cases, a electronic failure analysis engineer may not even lay eyes upon a failing device during the first step of the electonic failure analysis process – before beginning any work with the samples, it is often necessary to perform a little preliminary research. This initial review may consist of conversations with a customer, poring over datasheets, or reading through a device history, all in order to better understand the failing device – the conditions it was subjected to, the environment in which it was used, the amount of use the device received before failing, and so on. This initial investigation is crucial, as it allows the analyst to begin formulating hypotheses about potential failure mechanisms – which, in turn, can help to determine the course of the analysis going forward, by eliminating unnecessary tests and identifying techniques that present the best chance for uncovering the failure.

Once an electronic failure analysis lab analyst has researched the project sufficiently, the next step is to begin non-destructive testing of the failed electronic device. A course of non-destructive testing may be comprised of many different aspects – almost always, an in-depth optical inspection is performed to look for any obvious physical defects (e.g. cracked leads or encapsulant, burned circuit board traces, etc.). The optical inspection will often be supplemented by a high-resolution x-ray inspection to look for anomalies that may be hidden from view, like fused bond wires or voided solder. For failing integrated circuits, acoustic imaging may also be beneficial, allowing an analyst to detect delamination or other packaging anomalies that could be related to a failure. Just like the preliminary research, non-destructive testing often provides an analyst with crucial information that may dictate the entire course of the analysis. For example, many large microprocessors may have hundreds of connections between the package and the silicon die; if x-ray inspection can reveal that one of these bond wires has been fused, an analyst can immediately identify an area for further testing without needing to perform electrical characterization of the multitude of various inputs and outputs of the device, and to create a theory about the most likely cause of failure (since fusing a bond wire requires very high current, electrical overstress immediately shoots up to candidate #1).

After completing the non-destructive testing, the electronic failure analysis engineer must characterize and isolate the failure. The analyst must first confirm that the device is in fact failing in the reported fashion, by assembling an electrical test setup and exercising the part in the same way as reported by the customer. After the failure is confirmed, additional electrical characterization may be performed in an attempt to define the problem more narrowly (e.g. a problem reported as “output stuck high” may be translated into “output shorted to power supply through 100 ohms” with properly directed electrical characterization). With the device characterized, attempts to isolate the failure can begin – oftentimes, these tests are destructive in nature to varying degrees, since integrated circuits must be decapsulated, PCBs must have parts removed or traces cut, and so on. The techniques used to isolate the failure may be as technologically involved as thermal imaging or light emission microscopy, or as (relatively) simple as tracing a signal path using hand-held probe tips. The ultimate goal of the isolation step is to identify a site that can be investigated to reveal the root cause of the electronic device failure.

Finally, armed with the knowledge of an isolated location, the electronic failure analysis lab engineer can proceed to the final steps of the project. Depending on the type of failure, these steps may be wildly different – a cross-section might be necessary to identify damage between the layers of a printed circuit board, while an integrated circuit may require parallel deprocessing to uncover defects at the silicon substrate. The final steps of the analysis need not be destructive; often, elemental analysis is indicated, to determine the nature of a contaminant on a sample. Finally, with all analysis concluded, the analyst can write up the report, closing out their day… only to begin again anew tomorrow, with an entirely different set of challenges.

Derek Snider is a electronic failure analysis analyst at Insight Analytical Labs, where he has worked since 2004. He is currently an undergraduate student at the University of Colorado, Colorado Springs, where he is pursuing a Bachelors of Science degree in Electrical Engineering.


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