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Deprocessing – Unraveling the Intricacies of the Integrated Circuit

ic-fa-2At first glance, the modern integrated circuit may appear to be nothing more than a jumbled mess. Billions of transistors are connected to one another by a vast, labyrinthine network of metal traces, vias, wirebonds, and solder connections; a single electrical pulse may weave its way through countless other signals, moving through a spiraling spider’s web of conductors, before reaching its final destination at an output pin. For an analyst tasked with inspection or failure analysis of such a device, this convoluted system may resemble the proverbial Gordian knot. There is hope, however: just as Alexander was able to cut through the jumble of the fabled knot with his sword, an analyst skilled in deprocessing can slice through the tangles of circuitry, driving to the heart of the device under test.

On early integrated circuits, deprocessing was performed using wet-etch techniques. Several types of acids were used to remove the various oxides and metals present on the device, one layer at a time. As each layer was removed, an analyst could perform an inspection, looking for any processing defects that may be related to a failure (or, in the case of a reliability study, looking for anomalies that may lead to failure given enough time). These wet etch methods were effective on early semiconductor devices, where only two or three layers of metallic interconnects were necessary. As devices evolved and construction techniques changed, however, wet etch methods became much more risky due to the difficulty of etching a sample selectively, removing metals and dielectrics in a controlled fashion to allow for a comprehensive inspection.  To handle advanced parts, a different technique was necessary.

Parallel deprocessing (also referred to as lapping) replaces the acids used in wet-etch with an abrasive polish. The metals and oxides on the integrated circuit are slowly scrubbed away from the die, using a precisely calibrated polishing wheel and mounting assembly. Lapping may be augmented by reactive ion etching, a dry-etch technique that is capable of removing dielectrics in an extremely controlled fashion with very low risk of the accidental over-etch that can plague wet techniques. By slowly lapping away the layers of the device, an analyst can reveal features that may have been partially or completely obscured from their initial inspection. This facilitates inspection for possible reliability pitfalls, like metal thinning or via misregistration, or for damage that may indicate a failure.

By deprocessing a device judiciously and methodically, an analyst can unravel the intricate, convoluted network of interconnects that makes up a modern integrated circuit. In doing so, they can gather invaluable data about a sample, pertaining to anything from general construction parameters to information about a specific site where a failure occurred.

Derek Snider is a failure analyst at Insight Analytical Labs, where he has worked since 2004. He is currently an undergraduate student at the University of Colorado, Colorado Springs, where he is pursuing a Bachelors of Science degree in Electrical Engineering.

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