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Electronic Device Failure Analysis – Printed Circuit Board Delayering

                If one were able to take a modern printed circuit board and examine the vast network of metal traces, completely unobscured by dielectric materials, one would find an intricate, three-dimensional lacework of finely interwoven metal threads. Thin filaments of copper, reminiscent of a spider’s web, snake outward from ring-shaped vias, while in other places metallic tributaries flow into the large bus lines which carry rushing rapids of electrons that provide power to the devices on the board. The many layers of the board taken as a whole bring to mind a futuristic highway system, with thousands upon thousands of individual pathways crossing over one another, routing traffic seamlessly from point to point. Unfortunately, this highway system is not always perfect; thin filaments may break, rushing rapids of electrons may overflow, and improperly built pathways eventually fail, turning these intricate patterns into tangled snarls sure to frustrate any user. In these cases, electronic device failure analysis can help to unravel the tangled web that was woven; one of many approaches that may be taken in these scenarios is printed circuit board delayering.

                Printed circuit board delayering is an effective approach to electronic device failure analysis because it is one of a very few ways of examining a board as described above. PCB delayering is a close analogue to integrated circuit delayering; material is removed from the PCB using an abrasive polish, while an analyst maintains device planarity either through the use of specialized lapping equipment or, more commonly, finely calibrated fingers and a trained eye. The fiberglass weave and epoxy fill that make up the PCB dielectrics are generally removed in bulk with a polishing wheel and fine grit silicon carbide, with final touchup and spot polish performed by hand. Since metal lines are so tightly packed into small spaces, photographs of the delayered device must generally be augmented with optical microscopy; composite images of the board at relatively high magnification (between 50 and 200 times) are often required to show the level of detail necessary to find a defect. Different optical contrasting methods (e.g. bright-field and dark-field microscopy) are also useful, as some defects will appear much more clearly when viewed in a different light.

                Since printed circuit board delayering is a technique for electronic device failure analysis, it is important to recognize the types of defects that it is best for uncovering. Cracked or otherwise damaged traces are perfect candidates for PCB delayering, since the delayering process not only reveals the crack in the trace but also allows complete access to nodes on both sides of the crack, allowing an analyst to electrically probe the device and prove that the crack is the root cause of failure, creating an open circuit. Similarly, faults between two different traces on the same layer of a PCB can be identified by delayering and probed in the same fashion. Defects caused by electrical overstress are also easy to find with delayering, as the dielectric material near the failure site will often be discolored (or even blackened and burnt) as a result of the failure, giving the analyst performing the work an easy target. Defects occurring between layers of the board are not good candidates for PCB delayering, since the nature of the technique limits it to in-depth analysis of a single layer at a time; it is therefore vital to recognize the proper time for PCB delayering as opposed to other techniques.

                The inherent nature of printed circuit board delayering makes it a tool for inspecting relatively broad areas, as opposed to precisely targeted cross-sectional analysis. As such, it is often the preferred technique when focused isolation is not possible – open circuits, for example, are often much easier to find with delayering than with cross-section, since identifying the location of an open for cross-section in the absence of expensive time domain reflectometry equipment is difficult at best. Delayering is also indicated for large, distributed defects (e.g. a defect identified through thermal imaging as a large area of generalized heating as opposed to a pinpoint hot spot), since cross-section cannot generally capture such a defect in its entirety.

                While printed circuit board delayering is a handy tool for electronic device failure analysis, there are other applications as well. PCB delayering can provide invaluable data when qualifying new processes or suppliers as an avenue for directly measuring process parameters to ensure that specifications have been met; PCB delayering is also useful for reverse engineering endeavors, when patent infringement or other intellectual property concerns are suspected. Delayering is therefore an excellent addition to any analyst’s repertoire of tricks and techniques.

Derek Snider is a failure analysis engineer at Insight Analytical Labs, where he has worked since 2004. He received his Bachelor’s of Science in Electrical Engineering from the University of Colorado at Colorado Springs.

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