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Semiconductor and Electronic Failure Analysis Blog

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IC Failure Analysis Lab Flow – Defects From A to Z

IC failure analysis labTo someone unfamiliar with failure analysis of integrated circuits, it can be extremely difficult to imagine how any sort of meaningful data can be produced from a non-functioning piece of electronics – especially when the problem description is often phrased in nebulous terms, sprinkled heavily with empty words like “broken” and “defective”.  Yet, in many cases, a good analyst can turn these imprecise terms into a finely honed insight into a particular defect or device. One may ask how this is possible, given the extreme complexity of modern semiconductor devices. In IAL’s case, the answer lies in a well-planned IC failure analysis lab flow that takes a device from initial observations to final reporting.

One of the first steps taken on any project in the IC failure analysis lab is non-destructive testing – defined as any test that can be run without permanently altering the condition of the device. These tests may include x-ray imaging to look for fused or improperly formed bond wires, solder bridging, or other gross physical anomalies; oftentimes, acoustic microscopy will also be performed, looking for packaging anomalies or, in the case of newer, “flip-chip” style packaging, to look for malformed or disconnected die bumps. Generally speaking, while these tests are being run, one of IAL’s program managers will contact the customer requesting the analysis, in order to get a detailed history of the failing device (just like a doctor gathering a medical history on a patient) as well as to directly involve the customer, keeping them in the decision-making loop to ensure that their needs are being met.

Once the non-destructive testing (or NDT) has been performed and all data has been reviewed by the program manager, the device will be subjected to the tests and techniques that serve as the foundation for any IC failure analysis lab as it moves into the isolation phase. The device will be decapsulated to expose the semiconductor die inside, then subjected to the myriad variety of techniques at an analyst’s disposal – from relatively low-tech optical inspection to elaborate techniques involving a semiconductor’s unique responses to various external stimuli, no method is discounted as being without value for locating a defect.

Once a defect has been isolated, the device moves into its last stop in the IC failure analysis lab – deprocessing. Deprocessing specifically refers to the chore of stripping away the layers of metal and oxide on the failing device that conceal the defect from an analyst’s curious eye.  Depending on the nature of the defect, deprocessing may be forgone in lieu of a cross-section of the device, allowing an analyst to see any interactions between the layers of a failing device. Finally, a report is written and delivered to the customer, detailing any findings and providing the most likely cause of the device’s failure.

By following this type of failure analysis flow, IAL ensures that every project – no matter how esoteric – is approached methodically, offering the best chance for success in any FA endeavour.

Derek Snider is a failure analyst at Insight Analytical Labs, where he has worked since 2004. He is currently an undergraduate student at the University of Colorado, Colorado Springs, where he is pursuing a Bachelors of Science degree in Electrical Engineering.

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