Integrated Circuit (IC) Failure Analysis – Cutting Edge Trends
With the release of smaller, more feature-laden devices every year, it is obvious that the electronics industry is in a constant state of flux and evolution. The increase in complexity of a single integrated circuit over the years is undeniable, whether it is due to paradigm shifts in the methods of construction and operation or simply a result of the inexorable march of Moore’s law, which predicts that the number of transistors on integrated circuits will double roughly every two years.
Naturally, this constant change in technology has serious ramifications for failure analysis; a technique that was suitable for older products may not be sufficient for submicron technologies, with their densely-packed features and towering metal stacks. The failure analysis industry has therefore needed to respond quickly to changes in technology and develop new techniques capable of handling even the most complex of devices.
One of the most obvious effects the evolution of the integrated circuit has had on the electronic failure analysis process is the impact on inspection techniques. In many cases, a good optical microscope was sufficient for doing a large portion of an inspection; in some cases, even a detailed circuit extraction, a time consuming process involving hours at the microscope, tracing out individual signals to get a complete picture of the construction and function of a device.
As device features continue to shrink, however, optical microscopy is no longer sufficient; wave diffraction creates an absolute limit for the resolution of optical microscopy at roughly one-half the wavelength of visible light. In practical terms, this means that features smaller than roughly 200 nanometers cannot be correctly resolved with optical microscopy.
Electron microscopy failure analyisis is an obvious alternative, since the resolution limit for most modern tools is measured in tenths of nanometers – however, using electron microscopy for large-scale inspections, like those necessary for a circuit extraction, can be incredibly time and labor intensive, requiring a highly skilled operator and taking several hours in order to take all the necessary images for a successful inspection. As requests for this type of in-depth analysis have become an increasing trend in industry, it is necessary to find a way to meet the rising demand; IAL’s solution to this issue is to automate as much of the process as possible; by using software developed by the manufacturers of our optical and electron microscopes, it is possible for us to define an area of interest, set key parameters for the microscope and image, then walk away, allowing the microscope to autonomously bear the burden of collecting the library of photographs necessary for the IC failure analysis service to be completed.
The benefits of this type of system are immediately apparent; customers can get datasets with far more detail than were previously possible, while the impact to IAL’s workflow is much less than if a dedicated operator needed to man the tool for the whole inspection, allowing greater throughput (which in turn leads to happier customers, especially in an age where instantaneous information has become the expectation rather than the exception).
Another area in which the increased complexity of the integrated circuit failure analysis has caused issues is in the area of cross-sectional analysis. There are many trusted techniques for performing cross-sections that worked admirably for older devices: cleaved cross-sections, in which a device is scribed and broken at a site of interest, and mechanically ground cross-sections, in which abrasives are used to remove material from the die until the site of interest is reached, have both been successfully used for revealing defects for imaging. When the margin of error is expressed in nanometers as opposed to microns, however, these techniques begin to look almost barbaric – when the size of the defect is expected to be smaller than the finest polishing abrasive used in the cross-sectioning process, it is probably necessary to consider another approach. The problem of optical resolution is also convolved with the challenges of performing an integrated circuit cross-section; often, it will be necessary to target a single transistor, memory cell, or other similarly miniscule feature in order to uncover a defect.
The solution to this stymie can be found in the focused ion beam (or FIB), a tool similar to an electron microscope that is capable not only of imaging a device, but can also be used to remove material. Focused ion beams will often have built-in navigation systems that simplify the process of finding a cross-section site; an analyst need only load in the layout of the device (hopefully provided by an amicable, understanding customer) and perform a quick alignment, after which point it is possible to use the CAD model of the device to navigate. Cross-sectioning is as simple as defining the area of interest and creating an etch profile, then allowing the focused ion beam to slowly remove material until a defect has been uncovered. In reaction to the needs of the market, IAL has placed an order for a Dual-Beam FIB (a FIB which also incorporates a high resolution electron column for better imaging), which we will be taking delivery of in the beginning of 2013. We predict that this added capability will greatly increase our value to our customers and continue our reputation for fast, accurate analyses.
In essence, the overarching trend in integrated circuite (IC) failure analysis is that of increasing precision – more narrowly targeted isolation techniques, higher imaging resolution, and more accurately directed destructive methods are becoming necessary to work with modern devices. As a result, it is necessary to choose a lab committed to keeping up with the cutting edge technology that is becoming so prevalent, in order to help ensure the best outcome for a given analysis.
Derek Snider is a failure analyst at Insight Analytical Labs, where he has worked since 2004. He is currently an undergraduate student at the University of Colorado, Colorado Springs, where he is pursuing a Bachelors of Science degree in Electrical Engineering.