Using FIB for Wafer Lot acceptance and Design Verification
FIB (Focused Ion Beam) technology has certainly come a long way since its introduction in 1975. I recall very well the first encounter I had with the technology as a young ASIC designer in the late 80s. It seemed the most magical thing I had ever encountered: the ability to rework semiconductor devices, not only by being able to cut metallization lines (to correct shorts, for example, as had been done previously on a mechanical probe station), but also to add new conductive paths. FIB literally provided a designer the ability to add what are essentially blue wires to correct bugs in a design, as could be done with a board level product. FIB truly opened a whole new world.
In the early days, FIB machines were cantankerous, and required a tremendous level of skill and dedication to keep alive. The handful of good operators that existed were highly sought after, and comprised something of a brotherhood of alchemists. The chamber size on the early machines was small, the ability to image limited, and the control of the beam for cutting and deposition was somewhat crude, with manual control over the beam’s raster pattern provided by physical potentiometers.
I spent many hours in the company of one of those alchemists staring at the flickering green phosphor screen on an early Seiko FIB machine, looking for the telltale image bloom and screen washout that would occur when cutting through interlayer dielectrics and into the next conductive layer. And lo and behold: after a few hours of work, the prototype IC that was stillborn due to an error that I had made sprang to life. Magic!
With later generations of FIB hardware, it became possible to integrate voltage-contrast microscopy with the milling and deposition process, and integration of tester hardware allowed devices to be actually operated upon while running test vectors under normal operating conditions. Further development allowed the integration of the physical design database for the device into the navigation process, even allowing a specific node to be identified by name from a netlist, navigated to via the design database, imaged via voltage contrast, and then altered via FIB cuts or depositions- all in a single action.
This proved to be the designer’s best secret weapon for rapid debug and prototype bringup.
More than one design manager was heard to denigrate the benefits of FIB, stating that it made it “too easy to recover from mistakes that should never have been made in the first place”. However, FIB unquestionably saved the bacon of many a fallible designer, and its use has become commonplace.
The capabilities of modern FIB machines utterly overshadow the primitive capabilities I so revered from the 80s. In the current era of System-on-Chip (SoC) designs with 10 and 11 metal layers, copper metallizations, exotic dielectric materials, and the use of area pads scattered across the entire die area of a design, FIB provides an ideal diagnostic aid. It is even now possible to perform “backside FIB”, which involves milling into the die from the substrate side (as opposed to the top metal/passivation side). This allows the operator to avoid having to cut through multiple metal layers and complex, dense routing structures, and approach active devices from below.
Taken as a whole, these capabilities have proven to be a major boon for Electronic Failure Analysis processes. FA professionals can use the surgical precision afforded by the ion beam milling process to selectively strip back layers of overburden to reach and image very fine structures suspected of causing yield problems, infant mortality, or electromigration issues.
Exotic technologies such as Silicon-on-Insulator or III-V semiconductors pose little difficulty for modern FIB hardware. Similarly, advanced three-dimensional technologies such as FinFET or GAA (Gate All Around, or nanowire) transistor designs are handled quite well by modern FIB machines. Imaging and milling deposition resolutions have comfortably kept pace with technology steppings down to critical dimensions on the order of tens of nanometers, and the ion beam milling process is very compatible with fragile 3D structures. The technology provides debugging and diagnostic tools that were utterly unimaginable just a decade ago.
Insight Analytical Labs has built a sizable practice around its state of the art FEI Dual-Beam Field Emission Scanning Electron Microscope (FESEM), which provides FESEM functionality combined with a high resolution FIB capability in a single vacuum chamber. This unit allows IAL to section and image devices with resolutions down to 5nm. It can be used to prepare samples for transmission electron microscopy (TEM), and also incorporates a scanning TEM detector, allowing capture of much higher resolution images than possible with SEM alone. Further, its chamber is large enough to accept any packaged IC as well as wafers up to 6”, and its internal toolset allows many routine operations to take place entirely inside the chamber without breaking vacuum. It can perform many of the sample preparation, sectioning, and imaging tasks required for Wafer Lot Acceptance or other Failure Analysis tasks in a single pumpdown, saving a tremendous amount of time and expense.
Gone are the old pots on the front panel for beam control, replaced with a comprehensive software-driven user interface. However, I suspect that the operators still have a bit of the alchemist about them: notwithstanding any possible secret handshakes, they are still the wizards of debugging , bringup, and Failure Analysis in the brave new nanometer world. If it is small, expensive, exotic, and not functioning as it should: FIB can help.