If one were able to take a modern printed circuit board and examine the vast network of metal traces, completely unobscured by dielectric materials, one would find an intricate, three-dimensional lacework of finely interwoven metal threads. Thin filaments of copper, reminiscent of a spider’s web, snake outward from ring-shaped vias, while in other places metallic tributaries flow into the large bus lines which carry rushing rapids of electrons that provide power to the devices on the board. The many layers of the board taken as a whole bring to mind a futuristic highway system, with thousands upon thousands of individual pathways crossing over one another, routing traffic seamlessly from point to point. Unfortunately, this highway system is not always perfect; thin filaments may break, rushing rapids of electrons may overflow, and improperly built pathways eventually fail, turning these intricate patterns into tangled snarls sure to frustrate any user. In these cases, electronic device failure analysis can help to unravel the tangled web that was woven; one of many approaches that may be taken in these scenarios is printed circuit board delayering.