Wafer Lot Acceptance (MIL-STD-883 Method 2018)
Continuous monitoring of established processes to ensure that key parameters maintain within specifications is vital to ensuring process reliability. Even though a device may have been manufactured on a mature process, there is still a certain amount of parametric drift that can result in significant changes to the final product. Wafer Lot Acceptance (WLA) inspection is one way to help safeguard against this drift, by screening new production lots to look for anomalies that might negatively impact reliability.
IAL follows the procedure outlined in MIL-STD-883 Method 2018 for all Wafer Lot Acceptance inspections. Devices are deprocessed, layer-by-layer, with electron microscope images captured at each layer. An analyst will scan the die surface, looking for signs of improperly patterned metal; any anomalies are recorded, along with the worst case metal thinning noted. The device is also inspected at a high tilt to ensure sufficient metal step coverage; though this may seem an anachronism in the age of planar processing, certain defects appear more readily during the high-tilt inspection.
A cross-section is also performed as part of a Wafer Lot Acceptance inspection, to ensure that metal and dielectric thicknesses are within their specified ranges. The monitored parameters in a cross-section may include gate length, dielectric thicknesses between various active and metallization features, top glass thickness, step coverage into vias between metal layers, and many others. The cross-section is also one of the best ways to identify certain defects like unlanded vias that may not show up on a top-down inspection.
Electron micrograph of the polysilicon structures used to form MOSFET gates on an integrated circuit.
Electron micrograph of a cross-sectioned integrated circuit, examining metal step coverages of a 3 layer aluminum process.
Electron micrograph of logic circuitry on an integrated circuit.
Read more in our blog: Wafer Lot Acceptance to Mil-Std-883, Method 2018
While the MIL-STD for Wafer Lot Acceptance was clearly designed with older processes in mind, the procedure and techniques outlined therein remain applicable even to today’s cutting edge copper CMP devices. From legacy processes to the newest technology, WLA analysis can be performed on any integrated circuit.
- Continuous monitoring of an established process
- Qualification of a new device or process